LabVIEW Data Curve Fitting for MOSFET Parameter Extraction – Level 3 Spice

Sample curve fit here is for a measured transfer function (NMOS, grounded source), with stepping Vg and maintaining Vds=3 V. UO fits the sum of the points of the two curves and VTO, the slope of the difference.  The minimum current is selected to be consistent with strong inversion.

Block Diagram of the VI

Sum-Slope Computer – Scatter is from DAQ measurement.

UO Root Finder

Root Finder Loop

VTO Function

Note that VTO is initial value sensitive. Solution is VTO = 1.52 V for f = 0.

Iterate – Iteration variable vx in this case is UO.

Spice Level 3 Simulator

ETA Parameter is not included, as is effect from XJ not zero. UCRIT (VMAX)  dependence is on Vdsat and effective mobility due to velocity saturation (denominator in iD expression).  THETA effect is that from computing Vb from VC.

Slope For For KAPPA – Saturation

OC Fit For UCRIT – From velocity saturation effect in pre-saturation.

Initialization Computations

Some Parameters – NMOS – NXP HEF4007 CMOS

MOSFET Parameters with Implant

 

Implant MathCAD

 

 

 

 

 

Implant

Simulator Initializing Stage

 

Parameter Extraction – yd is adjusted to obtain required VFB, based on known implant dose.

Parameters with yd = 0. Effective implant voltage, Vd, is about o.14 V.

 

LabVIEW Cascode Amplifier Simulation compared with measured data.

MOSFET Simulation Parameter Determination from a Cascode Circuit

The measurement circuit for obtaining data for curve fitting is the following (LTspice). Input vg1 is stepped over a range to produce the desired range of drain  current. The drain current (from VRD), Vd1, and Vd2, are measured, thus Vgs2 and Vds2. The output characteristic is obtained from the circuit by stepping VDD over a range for a given vg1. The device is the Philips HEF4007 CMOS chip. Devices are M1, pins 6, 7, and 8 and M2, 9, 10, and 12. The simulator is the ekv v262 or equivalent.

Curve fitting parameter determination (M2) includes GAMMA, which provides NSUB, PHI. Curve fitting (M1) produces KP (UO), LAMBDA, and VFB (VTO). Separate adjustments are made to LETA and UCRIT, for best fits. Measured data (National Instruments DAQ and NI-DAQ) are stored in a Global Variable, as shown.

 

Example application is here, the function which fits the transfer characteristic for KP (sum) and VFB (slope of the difference).

 

Sum/Slope Computer – The function output (fslope or fsum) is the input to the Newton’s Method Root finder in the curve fitting process. The root-finder loop halts when these values reach a certain specified small value.

Sample Root Finder – KP – VFB and KP are carried as Global Variables to facilitate  passing along the updates. Note that in this case the plus and minus increments for the input variable (KP) are 100u with KP about 20 (uA).

Newton’s Method Iteration

Transfer Function Fit – KP and VFB – MAD is mean absolute point difference, percent.

 

M2 Transfer Characteristic – Sample GAMMA, NSUB.

With Curve Fit.

 

Output Characteristic Curve Fit

Simulator uses ekv channel-length modulation function and LETA function.

 

Simulated and Measured comparison.

 

Cascode Root Finder Functions (vd1 and vd2 iterations).

Basic Spice Level 3 LabVIEW Simulation

 

In these Global Variables are stored various core information, to be used as required.

This computation finds parameters, given NSUB. VTO is assigned as is later, UO and KAPPA. Parameter z is the channel-length modulation parameter. This is the NMOS example and the PMOS has a similar computation.

The complete, basic, level 3 simulation  is as given here.

SPICE Level 3 Model Circuit Design with Parameter Generation

 

K.L. Ashley

Analog Electronics with LabVIEW

The Level 3 Spice model used here is described in the following. (In the Process of additions.)

Level_3_SPICE

A  goal here is to demonstrate that the above model documentation is valid insofar as simulations fit precisely the simulations with LTspiceIV. LTspice Level 3 and Schematics (Microsim/OrCAD) are essentially identical. Simulation matches appear to call for a slightly altered value for the relative permittivity of silicon, and the choice of value has changed slightly over time.

Parameters: UO, VTO, KAPPA, NSUB, VMAX, THETA, XJ, RS, RD, and ETA.

Synthetic measured data –  equivalent are generated with a precision simulator. An example is shown here. TOX, GAMMA,  UCRIT, and VFB are selected to create the model functions. The example plotted here is for a P-well, tox = 100n, with this being the NMOS. Some numbers are below in the VI NMOS_Par_init. VFB is adjusted to simulate an implant. VTO and UO are obtained with a fit to the Xfer function (left plot, ID uA and VG) characteristic and KAPPA from the OC (ID uA, and VDS). TOX = 30 n. The drain-current magnitude suits the Level 3 model except for the OC pre-sat, but it is not used for curve fits. (N-well with implant reviewed below.)

An example curve fit (above plot) top, and simulator comparison follows. VMAX = 0.

Curve Fit Program

UCRIT is set essentially to infinity for VMAX = 0. The values shown are examples for the case of VMAX not zero.

DC Sweep of Common-Source Amp Stage -LabVIEW and LTspice

Circuit

VMAX non zero with LabVIEW and VMAX = 0 for LTspice

VMAX non Zero

OC

CS plus Source-Follower – LabVIEWVMAX non – Zero

N-well

The Level 3 parameters are now as indicated here. An implant of Vd = 0.5 V is included, to increase VTO of the NMOS and decrease that of the PMOS. Parameter is now tox = 30 n.

DCsweep – Top – LTspice and LabVIEW – Bottom – Common Source and Source follower

Voltage drop across SF M1 is reduced from above case. The gate width of SF MOSFETS is 10 times that of the CS. The load is 4 k Ohms and thus max load current is about 1 mA and minimum voltage out. The drain current must be set equal to zero at some point for negative voltage out for M1 since Level 3 is not valid for very low currents.

DC sweep of CS Stage – VMAX zero and VMAX non-zero

LabVIEW Simulator Sub – VMAX = 0 VDsat = Vdsat (velocity saturation effect)

VMAX non- zero – Vdsat  is 10 mV less that VDsat (VMAX zero)

SPICE Level 3 Model with LabVIEW and LTspice Simulation

 

K.L. Ashley

Analog Electronics with LabVIEW

The Level 3 Spice model used here is described in the following. (In the Process of additions.)

Level_3_SPICE

Parameters: UO, VTO, KAPPA, NSUB, VMAX, THETA, XJ, RS, RD, and ETA.

Parameters are extracted from the NMOS and PMOS from the NXP HEF4007UB CMOS chip. As in this example, shown are a parameter fit and a comparison between LabVIEW and LTspice. The example runs  Eq. 22, with only the first 4 parameters non-zero.

VMAX is now Non-Zero

Drain Current is Eq.  35.

Fit of measured data is not good around Vdsat, but LabVIEW and LTspice match.

MOSFET Amplifier Fundamentals – LabVIEW Simulation

Estimation of MOSFET Parameters for Circuit-Simulation

NMOS and PMOS Model Threshold Voltage and GAMMA for Simulator Model (EKV)

No Implant  – Neglect Interface Charge

VTO

P-Well – PMOS – NMOS Examples

N- Well PMOS – NMOS Examples

LAMBDA

Level_3

Use Level 3 to generate simulated measured data. Level 3 includes the P-N junction depletion-region function for channel-length modulation, thus, the doping dependence is taken into account. Obtain a curve fit with EKV to obtain LAMBDA. GAMMA and VTO  are from the above formulation. KP (mobility) is assigned a typical value.

All Parameters

CS with RD Common-Source Simulation with Above Parameters

VG is set for Vo=4 V with VDD=8 V. LAMBDA_N is launched in the background, which runs VT.

Iteration on VDS

VDD-VDS is applied across resistor. Iteration halts when NMOS simulator current and resistor current are equal. The three inputs to the NMOS simulator, top to bottom, are VG, VDS, and VS.

DC Sweep

The next circuit is a CS with active (PMOS) load, with circuit as given here. It includes the reference voltage circuit for the PMOS. (LTspice.) The bias current is the same as in the above circuit. The DC transfer is now more than doubled, plus the need for the load resistor is eliminated. The resistor in the bias circuit is external to the integrated circuit.

LabVIEW DC Transfer

CS + SF

The buffer stage allows for small loads without diminishing the gain.

DCSweep

CS

Output has been moved to 2.77 V, to set SF at zero Vo.

DCtransfer

CS gain is reduced at new bias point.

Optimize Gain with Gate Width

Analysis of the Maximum Voltage of OpAmp Output Stages with LabVIEW Simulator

Circuit

Shown is the output segment of the Op Amp with a standard, basic source-follower output stage, along the the common-source stage. The input to the CS is from the DiffAmp stage. This source-follower stage is later compared with the output stage of the TS271. The simulation is EKV and the parameter set is for an N substrate with P well (NMOS). The opposite is compared below.

VTO p = 1.25 V – VTO n = 1.51 V

Common-Source Stage

DCsweep – CS Output

CS Output at the Minimum

CS Drain Current about 20 uA at Op Pt

CS Output at Maximum

DC Sweep with SF Output

VGS(M2)=2.09 V.

RB=100 k for Larger Output Current

CS at Max Above

Op Pt CS Drain Current 90 uA. RL=1k for 6 mA output at max. Available output, 12 mA.

Sweep with and without Load

Compare with OpAmp with TS271 Output Stage

Source Follower Stage for Two Loads and Two Types

Standard SF – 1MEG load -IDM2 about equal to IDMn2

Standard Source Follower – RL=1 k, load current all from increase from M2.

TS271 Output Stage – RL=1MEG – negligible load current.

TS271 Output Stage – ID (M2) essentially unchanged (and thus, VGS(M2)). Feedback circuit reduces VGS (Mn2) to account for approximately 5 mA load current.

TS271 Output Circuit (LTspice)

Input to Mn2 is drain of M3.

Example 2

N-Well

VTO n=0.133  – V VTO p=2.45 V

DCsweep – Maximum is now limited by VGS(M3), which pushes VGS(MP) into pre-saturation.

Diffamp of output stage at max above. Note that VD(MP) is at 9.62 V

Analysis of the Common-Source Stage of the OpAmp with LabVIEW Simulation

Circuit, including output zero circuit.

Our LabVIEW balancing simulator gives the following, where the intersection is the solution for the output of the common-source stage (M9, M10). It finds Rset1 and Rset2. Note that the VD (3.52 V) solution is the drop across the source-follower output stage, the source of which is at zero volts. VDin is the DiffAmp output, and matches the DC sweep below.

The difference between the solution (intersection) and zero, is primarily the drop across the source-follower NMOS. The large value is a result of using parameters for the PMOS and NMOS from the CMOS switch chip. This is based on an N-type substrate (PMOS) and a P-well (NMOS). The large GAMMA associated with the large acceptor density of the well results in a large threshold voltage. At the end of this article, a switch will be made to the opposite, where the advantage is obvious.

DC sweep with Diff Amp Output

It is linear due to small range of voltage.

DC sweep for the amp output. Zero out at zero in.

OC plots at maximum out. Load PMOS is in pre-saturation.

OC plots at minimum. The PMOS plot is stationary, fixed by a given reference gate voltage (Mp from above circuit). The output can move to about -10 V.

Example for RB=500k, and RL=10 k. The output on the plus side is higher.

The next example is for the PMOS in the N-well. The threshold voltage of the NMOS is about zero. The maximum for positive output is increased significantly. The non-linearity at the negative end can  be attributed to the shape of the NMOS output characteristic (below) for low acceptor density of the substrate, which is included in the choice of parameters.

STMicroelectronics TS271 Operational Amplifier Analysis with LabVIEW

The analysis is based on our LabVIEW circuit simulator, which uses the EKV formulation. The parameters are obtained from curve fitting to PMOS and NMOS devices from the HEF4007US, information of which is available from the NXP logo in the right column. Gate widths for the various devices are based on mP and mM units, and mP=1 is 200u and mN=1 is 100u. The individual m units are selected for the desired current density, and are related to the EKV dimensionless current value, if, for example. (Reference in right column.)

Details are from the following: TS271. The version is created here, and reflects in general the core design of the OpAmp. The circuit is as follows. From input to output, the PMOS and NMOS reference-voltage circuit, the NMOS load differential amp circuit, the PMOS-load common-source stage and the output stage. The latter is a source follower except a special version, which includes a differential amplifier for providing feedback to the gate of the SF load (T16), such as to minimized the change of drain current in T15. A constant VGS15 (with changing drain current) represents a unity gain source-follower stage.

For simplicity, the reference circuit is the standard version, as in the following from LTspice. Similarly, initially, the source-follower stage is the basic version as given here, for comparison. Thus, it is the equivalent to eliminating all transistors beyond T8 and T9 above.

This amp has the opposite (PMOS and NMOS) differential and common-source stages.

Gates

Reference circuit, mP=mM=1.

DiffAmp, mP, mN=0.5, ID=25 uA.

Common-source, m(T6)=0.5, m(T7)=1, ID=50 uA (reference value).

Our simulator uses this balancing circuit: TS271

Differential Stage Simulator

VD2<VD1 due to balance. The potentiometer is set to  0.437 (0 to 1).

DCtransfer

DC sweep

Source follower at max in above plot. Approximately ID (RL)=8 mA.

Negative output.

Negative output with TS271 version of source follower. Note that VGS has dropped only to 1.64 V and the source-follower NMOS current down to 8 mA.

Zero output. VGS=1.76, for transfer ratio (negative) of 0.93. The simple case gives 0.83.

Comparison for positive output. Top: simple SF, ID SF NMOS = 23.3 mA, increasing from 15.6 for zero output. In plot below (TS271 stage), ID SF NMOS increases to only 16.7 at the given output voltage.

DC transfer over a wide range, top, standard SF, bottom, TS271. Smaller DC  transfer overall reflects the non-linear output of the open-circuit amp.