MOSFET SPICE Level 1 Circuit Simulation – LTspice/MathCAD – Opamp Frequency Response – Part 1

The project Opamp. Cascade of a diffamp, common-source, and source-follower stages. The power supply is from a sub-circuit and is plus and minus 2.5 V. Id (ms) and Id(m6, m7) are about 200 uA.

The Common-Source stage, which dominates frequency response. Gate resistor Rg is the output resistance of the diffamp stage. at the drains of m2 and m4..

Initially,  the capacitance of Level 1 LTspice (or PSpice Schematics) is matched with MathCAD for the case of a single pole, based on C1. Cc=Cgd  and C2 are for now made zero. Gate resistor Rg is the output resistance from the Diffamp stage. R2 is the combined  output resistance from m6 and m7. CL = C2 = 0.

Signal Circuit

MathCAD: Compute circuit current, Id.

 

Compute g Parameters. (Diffamp parameters computed elsewhere).

 

Compute C1, consistent with LTspice and PSpice. Assign a value to SPICE parameter cgso.  The first term in C1 is LTspice Level 1 default.

Plot common-source stage small-signal voltage gain versus frequency.

Phase Plot

LTspice

Include capacitor Cgd with parameter cgdo. This is Cc equivalent to the Opamp above, except internal to the NMOS, in this case. Make C2 = 1pF.

The gate-to-drain capacitor produces an additional pole and a zero, as computed here, which adds to phase shift. Also, the effective capacitor value is enhanced by the Miller effect.

Frequency Plot

LTspice