MOSFET Differential Amplifier Analysis with LVspiceIV and LabVIEW and EKV/Bucher et al.

The differential amplifier, from LTspiceIV, is as follows. For comparison to recent posts, the bias current (M1, etc.) is about 1mA.

A DC  sweep on VG1 is given here. The DC transfer around VG1=0 is 18.6.

The LabVIEW DC sweep is here. The slope is around VG1=0 and is based on 5 computational points of VG1=-15 mV to 15 mV.

The parameters obtained with LabVIEW extraction are as follows. LTspice uses the primary parameters and will not accept auxiliary alternatives such as NSUB. (These were modified after some fine tuning with LETA.)

More discussion will be added on the iterative solutions in the simulation. The model is based on node voltage in and drain current out, such that the node voltages are iterated to satisfy certain drain current requirements.

 

A new resistor with value R1=5k is used, resulting in lower bias currents. A LabVIEW gain finder is now used to estimate the new DC transfer, as shown here. The LTspice DC transfer is 22.1

 

The Diagram is shown here. The gate voltage is made plus and minus 5 mV, and the output is determined as shown.

 

The LabVIEW diffamp simulator follows. The iteration loop is on VS, i.e., the source voltage of the differential stage. The icon outside of the loop is the bias resistor/NMOS, which provides the bias voltage of M5. Icon Sim N simulates that stage, with a current output compared to the sum of the currents of the differential transistors. A match halts the iteration, with the required precision pre-set.

 

Bias circuit simulator follows. The resistor voltage is iterated. The resistor current is computed and compared to that of the NMOS, such that the iteration is halted when they match.

MOSFET Active-Load Differential Amplifier Simulated with LTspiceIV and LabVIEW

LTspiceIV circuit diagram is as follows. The bias resistor is selected for obtaining a similar transistor current as with the active-load CS amplifier, and a drain current, which is well within the Level 3 range. This is ID about 1mA.

A DC sweep shows the linear operating range and that the operating point output voltage is about 1V, which is VDD-VGPbias. The DC transfer for zero gate voltage is about 38, similar to the active load circuit for a similar bias.

The Top of the LabVIEW simulator is as follows. It uses two modules as shown below, which find solutions with  iteration. The loop halts when the resistor current and the sum of the MOSFET currents are equal. DC sweep from LabVIEW is below. Note that the transition to the limits is less abrupt.

DC Transfer is obtained with VG1=plus and minus 1mV. It produces 21.1.

The output characteristic slope is greater for the LabVIEW simulator, thus a higher gds, where the gain is inversely proportional to the sum of gdsn+gdsp. Examples for the NMOS with VG1=2.7V follow. Vdsat=0.674.

SPICE Level 3 Simulation of CMOS Active-Load Amplifier with LabVIEW Parameter Extraction

Various simulators exhibit different results for the Transfer Function (gain) of the active-load amplifier, due to a variation in computation of the saturation-region output resistance, as shown here, from LTspiceIV (Linear Technology). The goal is to compute the gain. First we need an operating-point gate voltage, VG1. It is found with a DC sweep as below, from LTspice. VG1=2.7V is picked. The DC transfer is 38.8, and 35.8 with Schematics, and 40.9 from AIM Spice.

Our simulation based on LabVIEW gives the following. The DC transfer is 24.1. The Active-load output pair solution is obtained in the loop below. VDS is iterated foe a drain-current match. The PMOS is biased with the VGS of the diode-connected PMOS.

The circuit is built using pins 12, 10, 11 for the bias PMOS, 13, 6, 14 for the output PMOS and 8, 6, 7 from another chip for the NMOS. We also connect a source follower from an additional chip using these pins (connected body-source) for later discussion. The measured result is in the following. The gain is considerably lower than given by the above Level 3 simulations. The parameters were obtained with the LabVIEW simulation model. There is of course a degree of variation between measured results from chip to chip, as the measurement is very sensitive to the chip characteristics.

Parameters are shown here.

Output characteristics are simulated and plotted below, using the LabVIEW simulator and LTspice. It is notable that they match in pre-saturation but the the slope is less for LTspice in the saturation region. Vdsat=0.674V.

The formulation for the saturation region used here is in the following:

 

SPICE Level 3 and LabVIEW Parameter Extraction for the PMOS Common-Source Amplifier

The schematics diagram is from Schematics (version from 2002).

A DC  sweep is from LTSpiceIV (Linear Technology). That from Schematics is essentially identical. The DC transfer is 5.38 and 5.31 from Schematics, for VG1=2.8V. AIM Spice has DC transfer of 5.36.

The LabVIEW simulation gives the following. DC transfer i s 5.30. Diagram is below.

The gm computer is as follows. It computes ID at the operating point voltage plus and minus 1mV.

The circuit is constructed and a sweep is made, with the results as follows. The PMOS is from pins 13, 6, and 14. This is the same device (NXP) as used in the measurement circuit, M1. The CS amp simply by-passes M2. The operating-point current is approximately 1mA, similar to the peak for the CMOS switch.

The Diagram for the measurement is as shown here. Slopes are obtained with LabVIEW Interpolate functions as given below. The icon VD_ID represents the two DAQ voltmeters for current and VDS.

The parameter extractor is  shown here. Note that XJ and ETA are non-zero for this case. A detailed outline of Spice Level 3 is here in the appendix. There is an error in the expression for Ep, which is essentially UCRIT. UO is from a fit to XF1 (sum), VFB (VTO) is from a fit to XF1 (slope), GAMMA (NSUB) is from a fit to XF2 (sum) and KAPPA is from a fit to the slope of OC1. OC1 is obtained by by-passing M2, to obtain a wide range of VDS, as in the amplifier. XJ, UCRIT (VMAX), and ETA are used to find a precision fit to all of these. The transfer-characteristic is made with a monotonically increasing VDS1 in order to obtain a range of surface potential values for the GAMMA measurement from X2.

SPICE Level 3 Simulation and LabVIEW Parameter Extraction for the NMOS Common-Source Amplfier

The Amplifier schematic is shown here from LTspiceIV (Linear Technology, cost-free down load.)

The Netlist: The output is at P001, drain of M1.

A DC sweep with LTspice yields the following. For Vo operating point of about 4V, we use VG1=2.6V. DC Transfer is -6.9.

A measured plot is as follows, along with the measured drain current. This is from pins 8, 6, and 7 from the chip.

The LabVIEW  simulation is as follows. Also computed and plotted is the slope and the DC transfer and slope for a cascaded source-follower stage.

Fundamentals of MOSFET Simulator Models

Comparison of Standard Model Form with Charge Integration in Depletion Region

The standard basis for the MOSFET model is as in the following. As will be discussed, the depletion-region charge is based on a depletion-region width with  uniform charge density from the substrate doping (depleted holes, NMOS). The channel electrons are treated as a charge sheet, which does not contribute to the surface potential. An excellent source of information on the following is from Yannis Tsividis. The basic principles are included in the appendix.

A sample simulation is shown as follows. For a given measured gate voltage, the surface potential is iterated until a match is obtained to the computed gate voltage.

The complete formulation is as follows. As noted, the surface potential is determined, which matches the computed gate voltage (below) to the measured value.

The channel charge and threshold voltage are obtained as in the following LabVIEW text interpreter program.

Pre-Beta current using a  standard simulator model is compared with the integration approach  as discussed here in the following.

In the next step, the holes are included in the depletion region, as indicated here. The functional form of the electric field changes, as does the depletion-region charge. The depletion-region charge is decreased, even with the increased length, and the channel charge increases as a trade-off.

The change in the current is shown below.

In the following is shown the result of including the electrons in the depletion-region charge. The change in the electric field form is evident at the surface. However, now all of the oxide charge is included as depletion-region charge, such that the change in the drain current is not considerable.

We verify the charge value obtained from the maximum electric field with and integration of the charge. The comparison is  here. Qdr is from the integration (of lower plot above) and QB is obtained from the electric field at the surface.

Standard Model Form and Charge Integration in the Depletion Region with Implant

Below is a MathCAD generated charge distribution for an idealized step implant. Implant depth is wi and depletion  width is wd. The implant is compensating.

First are shown computed plots of electric field and total charge. The step in charge is idealized, consistent with the above distribution. The x-axis for the implant region is scaled to match the electric fields at the transition, in effect, a constant of the integration. Electron and hole densities are not included in the field computation, consistent with the standard model. The maximum electric field (surface)  is sufficient for obtaining the depletion-region charge.

The next diagram shows the electric field function for the various cases.  The first function is for the conventional case of all depletion-region charges are from the substrate doping. The second example is sufficient for all cases in the substrate, outside of the implant region. The bottom is general (slightly approximate) and the middle term (holes)  can be dropped for the implant region.

A pre-Beta drain current comparison follows. The red plot is the precision standard model. It uses GAMMA and PHI based on the substrate.

The comparison here is now with the simulator modified by changing GAMMA and PHI to that corresponding to the implant region, where it applies to electrons.

A MathCAD except shows the possibility. This is the basis of the standard model. Note that “gi” and “PHIi” have been substituted in one place each, where it applies directly to electrons. Parameter “g” elsewhere applies to the depletion-region charge.

The ratio as shown below, though, is simply the ratio of the densities of impurities.

Thus, using the same GAMMA and PHI but multiplying the term by this ratio produces the same result. Our surface potential root finder (Newton’s Method), shown below, uses this. The “CC” expression is multiplied by “NR” as defined in the formulation.

Depletion-Region Oxide Voltage Approximate Form

At the core of many models is the elimination of the square-root term in the equation for the sum of gate voltages, beginning with SPICE 3. If the depletion region oxide voltage is in error, it is reflected in the value of the channel-oxide voltage, which is the key to the drain-current equations.

(In SPICE 3, the approximation is made at the end, following integration of the current equations using the precision form of the depletion-region oxide voltage. The result is the same.)

The following shows the depletion-region oxide voltage as computed with the approximate form and with the precision form, over a wide range of drain current, that is, input gate voltage, VG1, with VD1=1 V. The upper is an infinite series expansion of the lower.

The plots below are the Beta values over the range, computed from a measured drain-current match. We note that the approximate form (top) requires a higher Beta, corresponding to a smaller per-Beta current. Of course in modelling, this only leads to an (especially) artificial Beta, very standard in practice.

Three-Stage NMOS DC Amplifier on the HEF4007 Chip

K.L. Ashley

Analog Electronics with LabVIEW

We previously discussed stage simulation. This included the following cascode circuit.

Philips – HEF4007UB Inverter

This circuit can have high gains (for MOSFETS) as the output resistance is very high, such that the RD can be large. We now add the source follower stage as shown. Thus we have a cascade of a common-source, common gate, and common drain. The source follower (common drain) will not load the common-gate stage, and can handle large currents. Ideally the emitter follower (BJT) and source follower stages have unity gain but can be much less in real cases.

The signal circuit is as follows:

Bias solution for M3.

LabVIEW iteration Block Diagram.

Signal equation for av3.

Signal solution for Cascode.

A simulated gain plot follows. The cascode resistor is 10k, and thus not optimum, except at the highest current. The load resistor is 2k.

Design for a given resistor as follows. For 10k, pick ID to obtain VDS2 in the middle of the 5V range. Note the range is dictated by the approximate VGS2=5V for all currents. The choice is about 250 uA for a cascode gain of about 8.

In the following example is for 39k, the bias drain current is 60uA, for a cascode gain of about 15. Note that VD1=5V (for the VDD=10V example) such that VGS2=5V.

The 99k example shows that as drain current becomes smaller, the VGS2 value decreases a bit (VD1 increases) but VD1 remains at approximately 5 V. The design bias current is now 25 uA with a gain of 22.

The following is a simulation of gain with constant cascode drain-resistor voltage of 3 V. We plot the drain-source voltage of M2 to verify that ample signal-swing room exists. For a drain resistor of about 100k, the drain current is about 30 uA, with a gain of about 30.

We note that the drain of M1 (source of M2) is consistently about 5 volts, due to the body effect on the gate-source voltage of M2. Thus, with a 10 V VDD, there exists a balance of about 5 V for signal.

We construct an amplifier with RD=100k. Simulated plots of the voltage of the drain of M1 and the drain-voltage of M2 are shown, indicating that 25uA would allow maximum signal swing. A plot of measured and simulated gain is also given, for the same range of current. The design gate voltage is thus VG1=1.62V taken from the measured transfer characteristic.

We build a bias circuit for the gate of M1 using a 100k and a 20k resistor. (Approximate, VG1=1.65V.) The DAQ receiver then provides the results shown below. At this bias setting, the gain (cascode) is about 25. We note that the bias is not critical for staying in an operating range.

By manually (DAQ and LabVIEW) sending out increments of input volts (20 mV), we determine a gain av2=24 and Av=14.5 with a 10k load. Thus the transfer factor of the source follower is 0.604.

Simulation of Circuits – Cascode and CMOS Switch

K.L. Ashley

Analog Electronics with LabVIEW

DC and small-signal characteristics of the Cascode amplifier, the measurement circuit, and the CMOS switch will be simulated and and compared with measurements .  The device is:

Philips – HEF4007UB Inverter

The cascode circuit is shown here:

For comparison, we show the measurement circuit. The gate of M2 is moved to the drain of M2. In the following, it will be demonstrated that the gains are similar except for the negative feedback in the measurement circuit, between the gate and ground. This causes a substantial increase in the input resistance at the source of M2, and thus a loss of current to the output resistance of M1. The advantage of the measurement circuit for parameter extraction is that the drain-source voltage is is equal to the gate-source voltage and M2 is always in saturation.

The signal circuit for both is as follows. The feedback in the gate circuit of M2 is absent for the cascode.

The Block Diagram of the simulation for the measurement circuit is shown below.

The input nodes are the supply, V+, and the gate voltage, VG1. A transfer function is simulated with a range of values for VG1, with V+ set at a constant value, e.g., 8V.

At the initiation of the outside loop, a guess value for the drain current is sent to the resistor icon, to compute the drop across the resistor. This produces a value for VG2=VD2.  Next, the inside loop is initiated with the application of VG1. In response, M1 sends out a current to M2, approximate as VD1 is not yet known.

VDS2 is calculated for this current (icon M2).  Drain voltage VD2 minus VDS2 gives a new VD1. With this, a new drain current is calculated and this continues until VDS2 reaches a constant, final value. This completes the inside loop.

The new value of drain current is used to establish a new drop across Rm, giving a new VG2, to re-start the inside loop. The iteration continues until the value of drain current come to its final value, to halt the outside loop.

The diagram is similar for the cascode except V+ is connected to the gate of M2 and the drop across the drain resistor is is subtracted from V+ to obtain the drain voltage of M2.

 Circuit Gain

Transfer functions for the cascode and the measurement circuit with constant V+ (VDD) are obtained over a wide range of current. The assigned inputs VG1 (for each current) and V+ are supplied as inputs to the simulator to obtain the simulated bias node voltages.

To obtain measured gains, at each input VG1, the fractional index is found for VG1+40mV and VG1-40mV. The fractional index is then used to determine corresponding fractional outputs at VG2 and VD1 to obtain av and av1. The Block Diagram for this function is as follows.

Simulated gains are obtained by assigning an incremental plus and minus value to the input, except the incremental outputs are computed.

Comparison of the Measurement Circuit with the Cascode Circuit

The cascode circuit is repeated here. The gate of M2 is connected to the power supply. Both circuits use pins 6, 7 (ground), 8, 9, 10, and 12, referring to the pin diagram in the right column.

In the measurement circuit, the measurement resistor RM, produces a feedback in the gate circuit of M2,  which has the effect of increasing the input resistance of M2 at the source. The equation is shown in the following. The increased input resistance reduces the gain of the measurement circuit compared to the Cascode circuit, as shown. For comparison, the input resistance for the Cascode is also given.

The benefits of the cascode configuration is that the output resistance is very high and that even though the input at the source of M2 increases at the higher end of bias, it is still much less than the output resistance of M1, such that the overall transconductance remains approximately gm1.

A simulation for the gain for the two circuits is compared here.

The following shows the computed and measured transfer characteristic, drain voltage of M1 and gains av1 and av. The gain computations use simulated DC values.

We configure a low drain current cascode amplifier with a load of 277kOhms and VDD=10V. The gain curve is as follows. The signal gain is calculated without including an output resistance, while the results demonstrate that it is still negligible.

CMOS Simulation

The circuit is based on the CMOS on the right. Pin 10 is the input, and 12 is the output. The power supply of 5 V is pin 11. Pin 9 is ground. A small resistor (R=30 ohms) is in series with pin 11 for drain current measurement.

The Block Diagram for the simulation of the CMOS at one input  is as follows. For an assigned input, the loop computes ID  in sequence for the NMOS and PMOS, while iterating the output (drains) voltage. The loop halts when the currents are equal.

Measured and simulated  results are in the following. The parameters have been obtained by simulation, as in the clusters on the left.

With the CMOS circuit taken as a linear amplifier, we now evaluate the properties. From the CMOS simulation, we save the node voltages for the simulation. Then using the NMOS and PMOS model simulators the nominal gain is obtained in the output range with the slope in the saturation region (red line) for both transistors, in the example, -35. (The peak is higher but for an input of around 100mV, this number would be appropriate.) The simulators provide the output resistance, and those in parallel are also plotted as Ro. The forward transconductance is then obtained from the gain and Ro.

The standard configuration is as shown here, as taken from the Philips data sheet (link above). The bias resistor is large and sets the operating point. With a 5k load, the gain would be about 10. The average gm given in the data sheet for this supply voltage agrees with the results here.

 

CMOS Simulation with Basic Model (SPICE 3)

Static CMOS measurements are made and compared with a simulation based on the strong inversion model, Level 3. The effect of the implant is included with an implant voltage, Vd, added to the flatband voltage.  Beta (mobility) is assumed constant. The purpose of the implant is to move the effect threshold voltages of the NMOS (high) and PMOS (low) to a common value, such that the CMOS switching occurs near the middle of the voltage range.

The following link shows the derivation of Level 3.  The original version is based on a current integration with the standard form for the depletion-region oxide voltage, which leads to a 3/2 power term in surface potential (level 2). For level 3, this is eliminated with a Taylor series expansion of the these terms.  In this link, the expansion occurs, of the depletion-region expression,  before the integration. The results are identical.

Drain-Current_MODELS

Parameters are extracted for the devices in the saturation mode. The simulation equations for this case are given in the following. The parameters are VTO, GAMMA, Beta (KP), in addition to KAPPA, as discussed below.

Using an initial guess for GAMMA and KAPPA, parameters VTo and Beta are determined from the intercept and slope of a straight-line curve fit as in the following.

The measured data, from the following circuit, are a transfer function over a range of drain current (sweep VG1) corresponding to nominal strong inversion and that representative of the CMOS switch.  VD1=1V for all currents.

The LabVIEW VI block diagram for the extraction is as follows. XB is a global variable that contains the data. The ICON “FN Sig” computes the saturation region modulation factor and the ICON “FN PHI” calculates the intrinsic flatland voltage, VFB, based on GAMMA. The extraction of Beta and Vto is performed in a simple calculation by “FN_SIP_sub”. The pinchoff voltage VP used by “FN_sig” is also supplied by “FN_SIP_Sub”, as  shown in the Formula Node below.

The resulting data and simulation for the transfer functions for the NMOS and PMOS are as follows. In each case, GAMMA is adjusted for a common Vd, which is known. The values for VFB, and thus Vd, as calculated are in error from the use of PHI, as the actual flatband voltage at the bias levels of the transfer characteristic is larger. The fact that the fit in the case of the PMOS is not precise is an indication of the fact that Beta is not constant. Also, VTo will be in error from the fact that the drain current is only marginally in a state of strong inversion and that diffusion current is not negligible. Thus the parameters are somewhat artificial (in terms of the physical association) but function as required.

The channel-length modulation function is as follows. The parameter is KAPPA. The above curve fit is obtained initially with a guess KAPPA and then repeated with an iteration.

The parameters from the above files are passed to the CMOS simulator by way of a Global Variable. These are then used in the simulator as shown below, along with measured data.

We now use the simulator to investigate the state of the two transistors at various points in the switching process. In the first step, the input is Vin=1.94 V, the NMOS is active with a “load” from the PMOS, which is in pre-sat. Vo=4.9 V. Solution is for equal drain currents for both devices.

In the following step, Vi=2.34 V, and Vo=3.1, such VSD for the PMOS is 1.9 V, i.e., both transistors are active. Most of the switching occurs in this mode.

We move on to the opposite state, thus where the switch output is near zero. The NMOS is now the “load”, in pre-saturation, and the PMOS is active. The following drain-current function is thus the transfer characteristic for the PMOS with VSD about 5V.

The following shows a sweep from output high to low. A significant current still flows with the output nearly full off. The solution in all cases is where the currents are equal. NMOS goes from low to high, while the PMOS goes from high to low.