The Project Opamp
Power supplies, vdd=2.5 V and vss=-2.5 V, are from a sub-circuit. Compensating resistor Rc is initially zero.
DC Simulation with LabVIEW
Common-Source Stage, which dominates the frequency response of the opamp. Resistor rg is the small-signal output resistance of the diffamp stage.
Small-signal Circuit – Cc, Rc = 0
Compute Capacitance – Spice parameters cgso and cgdo. With an applied Cc, the intrinsic NMOS capacitance (Cgd) is added to the total. When Rc is non-zero, the gate-drain intrinsic value is neglected. The junction capacitance (Spice CJ, CJSW) is neglected (for example at the output drains) as it is expected that the external capacitance (at vo) will be large by comparison.
Frequency Transfer Function – Rc = 0 – Below, Rc not zero, with altered zero and additional pole wp3.
With all poles. Pole 3 is made arbitrarily large for Rc = 0.
Phase – Rc not zero.
Level 1 parameters, with capacitance parameters cgso and cgdo for NMOS. Capacitance at PMOS drain is neglected.
(Ref: Allen and Holberg, CMOS Analog Circuit Design, 2nd Edition. Oxford. Chap 3.)
Amplitude and Phase Plot – Include Feedback Factor, B = 1/10, with ideal feedback-amp gain of 10 (20 dB) as in mag plot. Find phase margin PM from phase plot as from curve fits. Cc and C2 = 0. Gain = 100 from diffamp stage is included, i.e., output is referred to Vin.
Pole-Zero computer. Indicated are intrinsic C1 and Cgd use here with SPICE Level 1.
Install C2 = 5 p at output.
Phase Margin drops to a low value with f2 decrease.
PM Root-Finder Computer
Signal circuit with Rc, Cc. Rc initially zero.
Pole, Zero computer.
Cc = 2 pF C2 = 5 pF
PM
Phase Margin versus Cc. This sweeps the PM Computer, above.
PSpice and LabVIEW Example – Cc = 2 pF, C2 = 1 pF.
Compensation with Rc
Compute Rc for setting the zero equal to pole Wp2. With Rc non-zero, the intrinsic Cgd is neglected.
Plot PM versus Cc.
Rc Compute – Cc and C2 assigned.
LabVIEW and LTspice
Kla's Blog 
Leave a comment