MOSFET SPICE Level 1 Circuit Simulation – PSpice/LTspice/LabVIEW – Design of Opamp Frequency Response – Part 3

Project Circuit

 

Gate length L = 2 um. The effects from Cc, Rb and m (m1 and m2) are investigated. Design compensating capacitor is initially Cc = 5 pF. Load CL = 10 pF. Level 1 parameters follow.

Small-Signal Model

Phase-Margin Computer

Parameter inputs include Rbias and m1, m2 gate width. Gate width for this case is W = 5 um (0.05 x 100 um). Computer finds frequency at av = 1 along with phase.

PM Computer Root Finder

Program av sub finds abdb = 0 (Decibels).

DC opamp simulator. Computes all DC info including that for gm, gds and small-signal low freq gains. Has inputs Rbias and m.

Pole – Zero Computer

 

Plots of characteristics.

Vary Rbias from 30 to 100 k. Plot versus Ids of ms (diffamp current source).

Vary gate width of diff amp m1 and m2 (gm).

 

Sample Response Plot – W1 = W2 = 5 um.

PSpice Schematics and LabVIEW

 

 

MOSFET SPICE Level 1 Circuit Simulation – PSpice/LTspice/LabVIEW – Opamp Frequency Response – Part 2

The Project Opamp

Power supplies, vdd=2.5 V and vss=-2.5 V, are from a sub-circuit. Compensating resistor Rc is initially zero.

DC Simulation with LabVIEW

Common-Source Stage, which dominates the frequency response of the opamp. Resistor rg is the small-signal output resistance of the diffamp stage.

Small-signal Circuit – Cc, Rc = 0

Compute Capacitance – Spice parameters cgso and cgdo. With an applied Cc, the intrinsic NMOS capacitance (Cgd) is added to the total. When Rc is non-zero, the gate-drain intrinsic value is neglected. The junction capacitance (Spice CJ, CJSW) is neglected (for example at the output drains) as it is expected that the external capacitance (at vo) will be large by comparison.

Frequency Transfer Function – Rc = 0 – Below, Rc not zero, with altered zero and additional pole wp3.

With all poles. Pole 3 is made arbitrarily large for Rc = 0.

Phase – Rc not zero.

Level 1 parameters, with capacitance parameters cgso and cgdo for NMOS. Capacitance at PMOS drain is neglected.

(Ref: Allen and Holberg, CMOS Analog Circuit Design, 2nd Edition. Oxford. Chap 3.)

 

Amplitude and Phase Plot – Include Feedback Factor, B = 1/10, with ideal feedback-amp gain of 10 (20 dB) as in mag plot. Find phase margin PM from phase plot as from curve fits. Cc and C2 = 0. Gain = 100 from diffamp stage is included, i.e., output is referred to Vin.

Pole-Zero computer. Indicated are intrinsic C1 and Cgd use here with SPICE Level 1.

Install C2 = 5 p at output.

Phase Margin drops to a low value with f2 decrease.

PM Root-Finder Computer

 

Signal circuit with Rc, Cc. Rc initially zero.

Pole, Zero computer.

Cc = 2 pF       C2 = 5 pF

PM

Phase Margin versus Cc. This sweeps the PM Computer, above.

PSpice and LabVIEW Example – Cc = 2 pF, C2 = 1 pF.

Compensation with Rc

Compute Rc for setting the zero equal to pole Wp2. With Rc non-zero, the intrinsic Cgd is neglected.

Plot PM versus Cc.

Rc Compute – Cc and C2 assigned.

LabVIEW and LTspice