Operational Amplifiers with LTspice

Opamp 1  – DiffAmp stage and common-source stage. Gain stages all have ID = 100 uA. Reference current is 50 uA. NMOS – W = 100 u PMOS – W = 200 u Relative Mrn – 0.5, Ms – 2, M3 – 1.

DC Transfer – Diff Amp

DC Transfer

LTspice DC Sweep – Output

Read Plot data with LabVIEW

DCsweep slope information computed from LTspice DCsweep data.

Signal Gain Compute

Diff Amp

Common-Source

Opamp 2 – PMOS Diffamp Opamp – Includes constant gm reference circuit. Opamp results are the same as with standard reference circuit at a given bias. Diffamp and Common-source gain stages have drain currents as in above circuit. Compare DC characteristics.

DCtransfer

Signal Gain

Parameter gdsn in diffamp is high (low output resistance) due to Vds being near saturation and the fact that the NMOS is in the substrate (versus the well). Parameter gm p is greater than gm n (cs) due to 2x relative W. Parameter gm p in above case is close to gm n but has 2 x the gate width in the PMOS.

Diff Amp

Common_Source

LTspice DCsweep

Plot data slopes.

Opamp 3 – NMOS current source diff amp with cascode-load common source. M1 is a common-gate stage with gate signal zero and bias from gate-drain of M4. M2 is a common-source stage with output resistance the input resistance of M1 and DC bias from M3. Gain stages have ID = 100 uA.

DCtransfer

Benefit comes from the fact that the NMOS has the lower output resistance.

Signal Gain

Cascode-stage gain.

Output resistance from drain of common-gate is 19 megOhms such that gain is approximately open-circuit gain of PMOS Mp1.

Computed slopes from LTspice DCsweep data.

Opamp 4 – Symmetrical output NMOS source diffamp, with symmetrical output.

DCtransfer – Vd2 – Input Diff Amp – Single Ended

DCtransfer

Signal Gain Computation  for Input Diffamp Stage – LabVIEW

Note low  output resistance of NMOS due to low Vds.

DCsweep – LTspice

Opamp 5 – PMOS Current Source Input Diffamp

DCtransfer – Vd2 – Input diff amp, single ended.

DCtransfer

Signal Gain – Diff Amp

Opamp 6 – Input Diffamp with Folded Cascode Load – Mp1 and Mp2 are in common-gate mode with ac ground at Vgr.

Diff Amp – Single Ended

DCtransfer

Opamp 7 – PMOS Input Diff Amp

Diffamp DCtransfer

DCtransfer

Read LTspice DCsweep – LabVIEW

Opamp 8 – Opamp 7 with npn cascode BJT devices.

Input configuration borrowed from LT 6240 opamp.

Read LTspice DCsweep.

Opamp 7 and 8 Comparison

Left column is for NMOS (M4 and M5) and the right column applies to the BJT (Q1 and Q2). Parameter rm in input resistance of common-gate or common base. Parameter fm, fb is portion of diff stage signal drain current which goes to output versus to Rb. Parameters rog and rob are resistances (megOhms) from cascode outputs. Parameters roM and roB are output resistances. Parameter rop is PMOS output resistance (megOhms) (M18 and M19). BJT case produces about 1.4 factor in higher DC transfer.

Basics of MOSFET Operational Amplifiers – LabVIEW and LTspice

The basic common-source gain stage to be considered is given here. The input voltage will be a compatible output voltage from a differential amplifier stage. The load is an NMOS current mirror, with voltage reference from diode-connected mnr.

A DCsweep from the LabVIEW simulator and LTspice is given here. The simulation is based on EKV v262. The reference current is about 50 uA and the common-source op pt current is approximately 100 uA with the relative gate width of mn1 and mnr equal to two.

The node voltages from the LV simulation are assigned Global Variables, such as shown  here in the signal gain computation. These are inputs to gm and gds computers, for obtaining the gain. Variable vd is the simulator solution, Vg is assigned and Vgn is the NMOS reference voltage. Results are below.

A basic op amp consists of reference-voltage circuit, a differential amplifier stage, and a common-source stage (as above) as given here. The PMOS reference is not used in this circuit. The diff amp stage provides for inverting and non-inverting inputs and zero input voltages (or common) at the op pt. It also provides for a compatible input for the common-source stage. Relative gate width of Mnr is 0.5 and that of Ms is 2. Thus a reference current of about 50 uA produces a current-source current from Ms of about 200 uA and a current in Mp2 of about 100 uA with a relative gate width of 1. With relative gate width of M4 also 1, the drain current her is also 100 uA. Relative gate width of M3 of 1 thus produces an output voltage of approximately unity.(300 mV).A typical set of parameters is produced by LabVIEW, based on a p-well configuration with NSUB = 0.1 x 10^22 for the NMOS and 1 x 10^22 for the PMOS. A common 0.7 V implant is assumed to bring the VTO for the two to a similar value. The parameters are sent by LabVIEW to a parameter file to be used by LTspice (below) (EKV simulator).

A DCsweep is performed by LTspice and a LabVIEW simulator as in the following. The two plots essentially coincide.

The simulation function for the top of the diff amp (Mp2 and Mn2) is shown here at the end of the iteration for zero op amp input. f1 is the difference between IDp and IDn and the end of convergence. Vd is the input voltage to the common-source stage.

Common-Source Stage

Voltage vd is the output from the common-source stage and is set to approximately zero.

LTspice data plot is read by LabVIEW for the above comparison.

DCsweep for Diff Amp Output

Signal Gain

Output conductance gds for the PMOS is high due to the drain voltage being close to Vdsat.

Sample output plots for the common-source stage (Vg opamp = 0). PMOS has Vsd = 0 from the right of the plot. The slope (saturation region) is greater for the NMOS, which is in the substrate.

At maximum of above DCsweep.

Minimum

Common-Source Stage with Cascode Mirror Circuit Load

The common source stage has the same PMOS driver but now a cascode NMOS load. We note that the PMOS has the higher output resistance. M1 is a common-gate stage with gate bias (ac ground) from M4. M2 is in a common-source configuration with source at ac ground a dc bias from M3. M1 has unit current transfer with an input resistance of 1/gm, thus very low. The source resistance of M1 is the output resistance of M2, such that, with source degeneration, the output resistance of M1 is rds1*rds2*gm1.

DCsweep

Signal Gain

Resistance in megOhms

Opamp

DCsweep

Opamp with wide-swing cascode load common-source.

Drain currents are 100 uA. Exception  is that in Rb, which is 50 uA. Current in Rb1 is 100 uA and gate width W of NMOS for Vgn reference (25 u) is 1/4 of cascode NMOS devices.M1, M2, M3, and M4 (100u). The difference between the larger reference Vgs and the rest is Vds2 and Vds3 which is about Vdsat.

Circuit includes buffer stage. DCsweep  is taken at common-source stage output.

DCsweep