Here is an output stage consisting of a basic source follower. Included is the common-source stage, from LTspice. With the 1Meg load, the DCtransfer is about- 60 (approximate CS stage gain), but with a 1k load, it is about -18. The simulator is ekv.
The subject alternative is shown below. This could have changed over time but the principle is the same. M1 and Mn1 are identified in both. An additional source follower is now the actual output (M2). The input to the output stage is connected to both source follower inputs, and the source-follower outputs (sources) are connected to the inputs of the differential stage.
Suppose vg2 is increased:
The transfer from source-follow of M1 will be very close to unity, with no load other than the load NMOS, Mn1. The source tracks the gate.
The source of M2 will increase by the increase by the change in vg2 but additionally falls by the increase of the VGS2 due to current drawn by the load RL.
The difference between the change of source voltage (negative) is applied to the non-inverting input of the differential amplifier, such that the output of the amplifier falls, dropping the current of Mn2, which accounts for most of the load current, such that the change in VGS2 is close to negligible, and hence, a nearly unity transfer function occurs.
The DCtransfer for this case computes to be 0.985. We increase the relative gate-width size of the two output transistors by a factor of 10 to obtain 0.992. The transfer is 0.985 now with a 1k load.
The effective transconductance is gm times the gain of the differential=amplifier stage. This partial circuit is used for a gain computation. This is -76 inverting and 69 non-inverting. With the large gate width, gm is about 1mA/V (based on our ekv parameters), or times the gain, 70mA/V. So 1V/mA x 70ma/V gives 70 for a gain of 70/71=0.986.
Numbers example.
delta vg2=1V with bias VG2=1.6V.
delta ID(M2)=29uA
delta ID(Mn2)=961uA
delta V(n005)=0.989
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