Analysis of the Maximum Voltage of OpAmp Output Stages with LabVIEW Simulator

Circuit

Shown is the output segment of the Op Amp with a standard, basic source-follower output stage, along the the common-source stage. The input to the CS is from the DiffAmp stage. This source-follower stage is later compared with the output stage of the TS271. The simulation is EKV and the parameter set is for an N substrate with P well (NMOS). The opposite is compared below.

VTO p = 1.25 V – VTO n = 1.51 V

Common-Source Stage

DCsweep – CS Output

CS Output at the Minimum

CS Drain Current about 20 uA at Op Pt

CS Output at Maximum

DC Sweep with SF Output

VGS(M2)=2.09 V.

RB=100 k for Larger Output Current

CS at Max Above

Op Pt CS Drain Current 90 uA. RL=1k for 6 mA output at max. Available output, 12 mA.

Sweep with and without Load

Compare with OpAmp with TS271 Output Stage

Source Follower Stage for Two Loads and Two Types

Standard SF – 1MEG load -IDM2 about equal to IDMn2

Standard Source Follower – RL=1 k, load current all from increase from M2.

TS271 Output Stage – RL=1MEG – negligible load current.

TS271 Output Stage – ID (M2) essentially unchanged (and thus, VGS(M2)). Feedback circuit reduces VGS (Mn2) to account for approximately 5 mA load current.

TS271 Output Circuit (LTspice)

Input to Mn2 is drain of M3.

Example 2

N-Well

VTO n=0.133  – V VTO p=2.45 V

DCsweep – Maximum is now limited by VGS(M3), which pushes VGS(MP) into pre-saturation.

Diffamp of output stage at max above. Note that VD(MP) is at 9.62 V

Analysis of the Common-Source Stage of the OpAmp with LabVIEW Simulation

Circuit, including output zero circuit.

Our LabVIEW balancing simulator gives the following, where the intersection is the solution for the output of the common-source stage (M9, M10). It finds Rset1 and Rset2. Note that the VD (3.52 V) solution is the drop across the source-follower output stage, the source of which is at zero volts. VDin is the DiffAmp output, and matches the DC sweep below.

The difference between the solution (intersection) and zero, is primarily the drop across the source-follower NMOS. The large value is a result of using parameters for the PMOS and NMOS from the CMOS switch chip. This is based on an N-type substrate (PMOS) and a P-well (NMOS). The large GAMMA associated with the large acceptor density of the well results in a large threshold voltage. At the end of this article, a switch will be made to the opposite, where the advantage is obvious.

DC sweep with Diff Amp Output

It is linear due to small range of voltage.

DC sweep for the amp output. Zero out at zero in.

OC plots at maximum out. Load PMOS is in pre-saturation.

OC plots at minimum. The PMOS plot is stationary, fixed by a given reference gate voltage (Mp from above circuit). The output can move to about -10 V.

Example for RB=500k, and RL=10 k. The output on the plus side is higher.

The next example is for the PMOS in the N-well. The threshold voltage of the NMOS is about zero. The maximum for positive output is increased significantly. The non-linearity at the negative end can  be attributed to the shape of the NMOS output characteristic (below) for low acceptor density of the substrate, which is included in the choice of parameters.

STMicroelectronics TS271 Operational Amplifier Analysis with LabVIEW

The analysis is based on our LabVIEW circuit simulator, which uses the EKV formulation. The parameters are obtained from curve fitting to PMOS and NMOS devices from the HEF4007US, information of which is available from the NXP logo in the right column. Gate widths for the various devices are based on mP and mM units, and mP=1 is 200u and mN=1 is 100u. The individual m units are selected for the desired current density, and are related to the EKV dimensionless current value, if, for example. (Reference in right column.)

Details are from the following: TS271. The version is created here, and reflects in general the core design of the OpAmp. The circuit is as follows. From input to output, the PMOS and NMOS reference-voltage circuit, the NMOS load differential amp circuit, the PMOS-load common-source stage and the output stage. The latter is a source follower except a special version, which includes a differential amplifier for providing feedback to the gate of the SF load (T16), such as to minimized the change of drain current in T15. A constant VGS15 (with changing drain current) represents a unity gain source-follower stage.

For simplicity, the reference circuit is the standard version, as in the following from LTspice. Similarly, initially, the source-follower stage is the basic version as given here, for comparison. Thus, it is the equivalent to eliminating all transistors beyond T8 and T9 above.

This amp has the opposite (PMOS and NMOS) differential and common-source stages.

Gates

Reference circuit, mP=mM=1.

DiffAmp, mP, mN=0.5, ID=25 uA.

Common-source, m(T6)=0.5, m(T7)=1, ID=50 uA (reference value).

Our simulator uses this balancing circuit: TS271

Differential Stage Simulator

VD2<VD1 due to balance. The potentiometer is set to  0.437 (0 to 1).

DCtransfer

DC sweep

Source follower at max in above plot. Approximately ID (RL)=8 mA.

Negative output.

Negative output with TS271 version of source follower. Note that VGS has dropped only to 1.64 V and the source-follower NMOS current down to 8 mA.

Zero output. VGS=1.76, for transfer ratio (negative) of 0.93. The simple case gives 0.83.

Comparison for positive output. Top: simple SF, ID SF NMOS = 23.3 mA, increasing from 15.6 for zero output. In plot below (TS271 stage), ID SF NMOS increases to only 16.7 at the given output voltage.

DC transfer over a wide range, top, standard SF, bottom, TS271. Smaller DC  transfer overall reflects the non-linear output of the open-circuit amp.

Design Detail of Basic Operational Amplifier

Version II   Our amplifier, from LTspice  is as follows. Factors affecting gain, bandwidth, and load-current capacity are considered. Simulator is EKV.

Initial design gives the following, from LabVIEW simulator. The gate width is specified in units, mP and mN, with all equal to 1 except for the source-follower output stage and for mP(M3) to balance the output.

DC Transfer Small-Signal Equivalent

DC Transfer

 The bandwidth for this case is 450kHz, from Schematics.

DC sweep for RL=5k, non-inverting.

SF output stage at max in above plot. About 9 mA available for load.

Common-source functions versus ID (RB). mP=1.4, mN=1, VDSP=8V, VDSN=12V. DC bias VGSP and VGSN are from amp bias circuit. Load is dominated by PMOS for both stages. ID common-source for above DC Transfer simulation is 30.9 uA.

Set

mN(MS)=0.5,

mN(M1,M2)=4,

nP(M11,M22)=8,

mN(M33)=0.5,

mP(M3)=9.3 for balanced zero output.

RL=500k. DC Transfer:

Circuit voltages and currents.

New bandwidth, 87 kHz.

Maximum negative voltage for RL=1k, and ID (RL)=6.4 mA. The load current  is supplied by M44 such that VGS4 rises to 1.55 V, the result being a non-unity gain output stage.

Reduce reference current resistor to RB=250 kOhms. Now have 15 mA into 500 Ohm load.

DC sweep for RB=50 k, RL=100 Ohms. Max negative load current is 60 mA.

DC Transfer – Bandwidth=420 kHz

Amp  with Negative Feedback

DC Transfer -Ideal Limit = 101

Resistance Feedback Operational Amplifier Primer

The sample amplifier, for discussion, is the standard basic op amp. The TS271 unit-gain source follower output stage will be added. Initially is shown the LabVIEW-simulator op  amp. The gate width of M7 and M8 (common-source stage, LTspice circuit below) are adjusted to place the open  circuit output (source-follower source) near zero volts. The three stage DC outputs are indicated on the right. Bias resistor RB gives a relatively high bias current in this case.

The source-follower simulator shows currents and voltages. The gate widths have been made large for a bias current of  on the order of several miliamps.

The DC transfer (inverting) is measured for plus and minus VG2, the non-inverting input. It is noted to be non-linear, as expected, for output moving through about 5V  for this 1mV range of inputs.

A sample for a larger RB.

Op Amp with TS271 output stage:

Bias resistor is increased to 400k for a reference current of 46uA. Note that the transfer ratio of the feedback-source follower stage is close to unity.

Lower reference current and the effect of gain.

Inverting Resistance Feedback Amplifier

Shown here is the op amp with standard source-follower output, which has the feedback network. Rf=100k and Rg=1k, such that the ideal gain is 101.

Gain calculation summary is as follows.

Simulator with results is here. The above result has the open circuit gain adjusted to fit the result below.

Op Amp feedback iteration VI. For VG2=1mV, the feedback network installs about 1.10mV at the gate, such that the gate difference times the open circuit gain produces the output, Vo=120mV.

Minus input. Gates voltage difference is 20.9uV for the sum of 200mV out, for an internal transfer of about 9000. The gain is the 200mV out divided by the 2mV (net, VG1) in.

Es geht weiter.

Unity-Gain Source-Follower Output Stage of the STMicroelectronics TS271 MOSFET Opamp

Here is an output stage consisting of a basic source follower. Included is the common-source stage, from LTspice. With the 1Meg load, the DCtransfer is about- 60 (approximate CS stage gain), but with a 1k load, it is about -18. The simulator is ekv.

The subject alternative is shown below. This could have changed over time but the principle is the same. M1 and Mn1 are identified in both. An additional source follower is now the actual output (M2).  The input to the output stage is connected to both source follower inputs, and the source-follower outputs (sources) are connected to the inputs of the differential stage.

Suppose vg2 is increased:

The transfer from source-follow of M1 will be very close to unity, with no load other than the load NMOS, Mn1. The source tracks the gate.

The source of M2 will increase by the increase by the change in vg2 but additionally falls by the increase of the VGS2 due to current drawn by the load RL.

The difference between the change of source voltage (negative) is applied to the non-inverting input of the differential amplifier, such that the output of the amplifier falls, dropping the current of Mn2, which accounts for most of the load current, such that the change in VGS2 is close to negligible, and  hence, a nearly unity transfer function occurs.

The DCtransfer for this case computes to be 0.985. We increase the relative gate-width size of the two output transistors by a factor  of 10 to obtain 0.992. The transfer is 0.985 now with a 1k load.

The effective transconductance is gm times the gain of the differential=amplifier stage. This partial circuit is used for a gain computation. This is -76 inverting and 69 non-inverting. With the large gate width, gm is about 1mA/V (based on our ekv parameters), or times the gain, 70mA/V. So 1V/mA x 70ma/V gives 70 for a gain of 70/71=0.986.

Numbers example.

delta vg2=1V with bias VG2=1.6V.

delta ID(M2)=29uA

delta ID(Mn2)=961uA

delta  V(n005)=0.989

NMOS Common-Source Source-Follower Amplifier Evaluation

The circuit is constructed for testing from the chip. Both transistors use pins 6, 7, and 8 without body effect and the CS uses 6, 7, and 8 and the SF uses 3, 4, and 5 for the BE case, as would be necessary for the total amp coming from one chip.

The measured DC sweep for without and with BE  are here.

The Simulations follow,including DCtransfer. The DC transfer is reduced by BE.

SF simulations at the op pt VG=1.75V are given here. The DC VGS=4.64 volts, due to BE, for the latter case.  The op pt ID is 1.7mA for the firsts case, with the 1k load.

The Gate  width of  the SF NMOS is now made 20 times that of the CS, with the following. The VGS of the SF is now down significantly and the DCtransfer loss across the SF  is relatively small.

The larger DC output also permits a large bias VGS1, along with an improved DC transfer, as in the following.

The small-signal gain computation gives the same result for CS stage, as shown here.

DC sweep from LTspice, VD CS.

DCtransfer from Multisim

Multisim DCsweep, VD CS