CMOS Simulation with Level 3 Spice – Part 2

In a previous post, VTO was obtained by a data intercept. Here, we will use a slope fit to the Transfer Characteristic (wide range of ID with constant VDS). The comparison is here for the NMOS. VTO now is allowed to vary with the selection of other parameters, and is a reflection of the fact that the actual case departs from the simple case.

The simulated CMOS response for three of the available samples is given here.

The three parameters, with GAMMA assigned, are shown here. UO is the sum fit to the transfer function, VTO is a slope fit, and KAPPA is a slope fit to the output characteristic. VMAX, ETA, can be assigned.

UCRIT= 1M (VMAX=44k) produces the lower output characteristic here (NMOS), with improved pre-sat fit, while the upper is without velocity saturation included (typical of the basic Level 3). Note that this is otherwise not the standard version of Level 3 with VMAX not zero, but rather only includes the affect on UO from velocity saturation.

Measured and simulation plots of the three samples are here.