Various simulators exhibit different results for the Transfer Function (gain) of the active-load amplifier, due to a variation in computation of the saturation-region output resistance, as shown here, from LTspiceIV (Linear Technology). The goal is to compute the gain. First we need an operating-point gate voltage, VG1. It is found with a DC sweep as below, from LTspice. VG1=2.7V is picked. The DC transfer is 38.8, and 35.8 with Schematics, and 40.9 from AIM Spice.
Our simulation based on LabVIEW gives the following. The DC transfer is 24.1. The Active-load output pair solution is obtained in the loop below. VDS is iterated foe a drain-current match. The PMOS is biased with the VGS of the diode-connected PMOS.
The circuit is built using pins 12, 10, 11 for the bias PMOS, 13, 6, 14 for the output PMOS and 8, 6, 7 from another chip for the NMOS. We also connect a source follower from an additional chip using these pins (connected body-source) for later discussion. The measured result is in the following. The gain is considerably lower than given by the above Level 3 simulations. The parameters were obtained with the LabVIEW simulation model. There is of course a degree of variation between measured results from chip to chip, as the measurement is very sensitive to the chip characteristics.
Parameters are shown here.
Output characteristics are simulated and plotted below, using the LabVIEW simulator and LTspice. It is notable that they match in pre-saturation but the the slope is less for LTspice in the saturation region. Vdsat=0.674V.
The formulation for the saturation region used here is in the following:
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