MOSFET Differential Amplifier Analysis with LVspiceIV and LabVIEW and EKV/Bucher et al.

The differential amplifier, from LTspiceIV, is as follows. For comparison to recent posts, the bias current (M1, etc.) is about 1mA.

A DC  sweep on VG1 is given here. The DC transfer around VG1=0 is 18.6.

The LabVIEW DC sweep is here. The slope is around VG1=0 and is based on 5 computational points of VG1=-15 mV to 15 mV.

The parameters obtained with LabVIEW extraction are as follows. LTspice uses the primary parameters and will not accept auxiliary alternatives such as NSUB. (These were modified after some fine tuning with LETA.)

More discussion will be added on the iterative solutions in the simulation. The model is based on node voltage in and drain current out, such that the node voltages are iterated to satisfy certain drain current requirements.

 

A new resistor with value R1=5k is used, resulting in lower bias currents. A LabVIEW gain finder is now used to estimate the new DC transfer, as shown here. The LTspice DC transfer is 22.1

 

The Diagram is shown here. The gate voltage is made plus and minus 5 mV, and the output is determined as shown.

 

The LabVIEW diffamp simulator follows. The iteration loop is on VS, i.e., the source voltage of the differential stage. The icon outside of the loop is the bias resistor/NMOS, which provides the bias voltage of M5. Icon Sim N simulates that stage, with a current output compared to the sum of the currents of the differential transistors. A match halts the iteration, with the required precision pre-set.

 

Bias circuit simulator follows. The resistor voltage is iterated. The resistor current is computed and compared to that of the NMOS, such that the iteration is halted when they match.

MOSFET Active-Load Differential Amplifier Simulated with LTspiceIV and LabVIEW

LTspiceIV circuit diagram is as follows. The bias resistor is selected for obtaining a similar transistor current as with the active-load CS amplifier, and a drain current, which is well within the Level 3 range. This is ID about 1mA.

A DC sweep shows the linear operating range and that the operating point output voltage is about 1V, which is VDD-VGPbias. The DC transfer for zero gate voltage is about 38, similar to the active load circuit for a similar bias.

The Top of the LabVIEW simulator is as follows. It uses two modules as shown below, which find solutions with  iteration. The loop halts when the resistor current and the sum of the MOSFET currents are equal. DC sweep from LabVIEW is below. Note that the transition to the limits is less abrupt.

DC Transfer is obtained with VG1=plus and minus 1mV. It produces 21.1.

The output characteristic slope is greater for the LabVIEW simulator, thus a higher gds, where the gain is inversely proportional to the sum of gdsn+gdsp. Examples for the NMOS with VG1=2.7V follow. Vdsat=0.674.

SPICE Level 3 Simulation of CMOS Active-Load Amplifier with LabVIEW Parameter Extraction

Various simulators exhibit different results for the Transfer Function (gain) of the active-load amplifier, due to a variation in computation of the saturation-region output resistance, as shown here, from LTspiceIV (Linear Technology). The goal is to compute the gain. First we need an operating-point gate voltage, VG1. It is found with a DC sweep as below, from LTspice. VG1=2.7V is picked. The DC transfer is 38.8, and 35.8 with Schematics, and 40.9 from AIM Spice.

Our simulation based on LabVIEW gives the following. The DC transfer is 24.1. The Active-load output pair solution is obtained in the loop below. VDS is iterated foe a drain-current match. The PMOS is biased with the VGS of the diode-connected PMOS.

The circuit is built using pins 12, 10, 11 for the bias PMOS, 13, 6, 14 for the output PMOS and 8, 6, 7 from another chip for the NMOS. We also connect a source follower from an additional chip using these pins (connected body-source) for later discussion. The measured result is in the following. The gain is considerably lower than given by the above Level 3 simulations. The parameters were obtained with the LabVIEW simulation model. There is of course a degree of variation between measured results from chip to chip, as the measurement is very sensitive to the chip characteristics.

Parameters are shown here.

Output characteristics are simulated and plotted below, using the LabVIEW simulator and LTspice. It is notable that they match in pre-saturation but the the slope is less for LTspice in the saturation region. Vdsat=0.674V.

The formulation for the saturation region used here is in the following:

 

SPICE Level 3 and LabVIEW Parameter Extraction for the PMOS Common-Source Amplifier

The schematics diagram is from Schematics (version from 2002).

A DC  sweep is from LTSpiceIV (Linear Technology). That from Schematics is essentially identical. The DC transfer is 5.38 and 5.31 from Schematics, for VG1=2.8V. AIM Spice has DC transfer of 5.36.

The LabVIEW simulation gives the following. DC transfer i s 5.30. Diagram is below.

The gm computer is as follows. It computes ID at the operating point voltage plus and minus 1mV.

The circuit is constructed and a sweep is made, with the results as follows. The PMOS is from pins 13, 6, and 14. This is the same device (NXP) as used in the measurement circuit, M1. The CS amp simply by-passes M2. The operating-point current is approximately 1mA, similar to the peak for the CMOS switch.

The Diagram for the measurement is as shown here. Slopes are obtained with LabVIEW Interpolate functions as given below. The icon VD_ID represents the two DAQ voltmeters for current and VDS.

The parameter extractor is  shown here. Note that XJ and ETA are non-zero for this case. A detailed outline of Spice Level 3 is here in the appendix. There is an error in the expression for Ep, which is essentially UCRIT. UO is from a fit to XF1 (sum), VFB (VTO) is from a fit to XF1 (slope), GAMMA (NSUB) is from a fit to XF2 (sum) and KAPPA is from a fit to the slope of OC1. OC1 is obtained by by-passing M2, to obtain a wide range of VDS, as in the amplifier. XJ, UCRIT (VMAX), and ETA are used to find a precision fit to all of these. The transfer-characteristic is made with a monotonically increasing VDS1 in order to obtain a range of surface potential values for the GAMMA measurement from X2.

SPICE Level 3 Simulation and LabVIEW Parameter Extraction for the NMOS Common-Source Amplfier

The Amplifier schematic is shown here from LTspiceIV (Linear Technology, cost-free down load.)

The Netlist: The output is at P001, drain of M1.

A DC sweep with LTspice yields the following. For Vo operating point of about 4V, we use VG1=2.6V. DC Transfer is -6.9.

A measured plot is as follows, along with the measured drain current. This is from pins 8, 6, and 7 from the chip.

The LabVIEW  simulation is as follows. Also computed and plotted is the slope and the DC transfer and slope for a cascaded source-follower stage.