K.L. Ashley
Analog Electronics with LabVIEW
We previously discussed stage simulation. This included the following cascode circuit.
This circuit can have high gains (for MOSFETS) as the output resistance is very high, such that the RD can be large. We now add the source follower stage as shown. Thus we have a cascade of a common-source, common gate, and common drain. The source follower (common drain) will not load the common-gate stage, and can handle large currents. Ideally the emitter follower (BJT) and source follower stages have unity gain but can be much less in real cases.
The signal circuit is as follows:
Bias solution for M3.
LabVIEW iteration Block Diagram.
Signal equation for av3.
Signal solution for Cascode.
A simulated gain plot follows. The cascode resistor is 10k, and thus not optimum, except at the highest current. The load resistor is 2k.
Design for a given resistor as follows. For 10k, pick ID to obtain VDS2 in the middle of the 5V range. Note the range is dictated by the approximate VGS2=5V for all currents. The choice is about 250 uA for a cascode gain of about 8.
In the following example is for 39k, the bias drain current is 60uA, for a cascode gain of about 15. Note that VD1=5V (for the VDD=10V example) such that VGS2=5V.
The 99k example shows that as drain current becomes smaller, the VGS2 value decreases a bit (VD1 increases) but VD1 remains at approximately 5 V. The design bias current is now 25 uA with a gain of 22.
The following is a simulation of gain with constant cascode drain-resistor voltage of 3 V. We plot the drain-source voltage of M2 to verify that ample signal-swing room exists. For a drain resistor of about 100k, the drain current is about 30 uA, with a gain of about 30.
We note that the drain of M1 (source of M2) is consistently about 5 volts, due to the body effect on the gate-source voltage of M2. Thus, with a 10 V VDD, there exists a balance of about 5 V for signal.
We construct an amplifier with RD=100k. Simulated plots of the voltage of the drain of M1 and the drain-voltage of M2 are shown, indicating that 25uA would allow maximum signal swing. A plot of measured and simulated gain is also given, for the same range of current. The design gate voltage is thus VG1=1.62V taken from the measured transfer characteristic.
We build a bias circuit for the gate of M1 using a 100k and a 20k resistor. (Approximate, VG1=1.65V.) The DAQ receiver then provides the results shown below. At this bias setting, the gain (cascode) is about 25. We note that the bias is not critical for staying in an operating range.
By manually (DAQ and LabVIEW) sending out increments of input volts (20 mV), we determine a gain av2=24 and Av=14.5 with a 10k load. Thus the transfer factor of the source follower is 0.604.
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