K.L. Ashley
Analog Electronics with LabVIEW
DC and small-signal characteristics of the Cascode amplifier, the measurement circuit, and the CMOS switch will be simulated and and compared with measurements . The device is:
The cascode circuit is shown here:
For comparison, we show the measurement circuit. The gate of M2 is moved to the drain of M2. In the following, it will be demonstrated that the gains are similar except for the negative feedback in the measurement circuit, between the gate and ground. This causes a substantial increase in the input resistance at the source of M2, and thus a loss of current to the output resistance of M1. The advantage of the measurement circuit for parameter extraction is that the drain-source voltage is is equal to the gate-source voltage and M2 is always in saturation.
The signal circuit for both is as follows. The feedback in the gate circuit of M2 is absent for the cascode.
The Block Diagram of the simulation for the measurement circuit is shown below.
The input nodes are the supply, V+, and the gate voltage, VG1. A transfer function is simulated with a range of values for VG1, with V+ set at a constant value, e.g., 8V.
At the initiation of the outside loop, a guess value for the drain current is sent to the resistor icon, to compute the drop across the resistor. This produces a value for VG2=VD2. Next, the inside loop is initiated with the application of VG1. In response, M1 sends out a current to M2, approximate as VD1 is not yet known.
VDS2 is calculated for this current (icon M2). Drain voltage VD2 minus VDS2 gives a new VD1. With this, a new drain current is calculated and this continues until VDS2 reaches a constant, final value. This completes the inside loop.
The new value of drain current is used to establish a new drop across Rm, giving a new VG2, to re-start the inside loop. The iteration continues until the value of drain current come to its final value, to halt the outside loop.
The diagram is similar for the cascode except V+ is connected to the gate of M2 and the drop across the drain resistor is is subtracted from V+ to obtain the drain voltage of M2.
Circuit Gain
Transfer functions for the cascode and the measurement circuit with constant V+ (VDD) are obtained over a wide range of current. The assigned inputs VG1 (for each current) and V+ are supplied as inputs to the simulator to obtain the simulated bias node voltages.
To obtain measured gains, at each input VG1, the fractional index is found for VG1+40mV and VG1-40mV. The fractional index is then used to determine corresponding fractional outputs at VG2 and VD1 to obtain av and av1. The Block Diagram for this function is as follows.
Simulated gains are obtained by assigning an incremental plus and minus value to the input, except the incremental outputs are computed.
Comparison of the Measurement Circuit with the Cascode Circuit
The cascode circuit is repeated here. The gate of M2 is connected to the power supply. Both circuits use pins 6, 7 (ground), 8, 9, 10, and 12, referring to the pin diagram in the right column.
In the measurement circuit, the measurement resistor RM, produces a feedback in the gate circuit of M2, which has the effect of increasing the input resistance of M2 at the source. The equation is shown in the following. The increased input resistance reduces the gain of the measurement circuit compared to the Cascode circuit, as shown. For comparison, the input resistance for the Cascode is also given.
The benefits of the cascode configuration is that the output resistance is very high and that even though the input at the source of M2 increases at the higher end of bias, it is still much less than the output resistance of M1, such that the overall transconductance remains approximately gm1.
A simulation for the gain for the two circuits is compared here.
The following shows the computed and measured transfer characteristic, drain voltage of M1 and gains av1 and av. The gain computations use simulated DC values.
We configure a low drain current cascode amplifier with a load of 277kOhms and VDD=10V. The gain curve is as follows. The signal gain is calculated without including an output resistance, while the results demonstrate that it is still negligible.
CMOS Simulation
The circuit is based on the CMOS on the right. Pin 10 is the input, and 12 is the output. The power supply of 5 V is pin 11. Pin 9 is ground. A small resistor (R=30 ohms) is in series with pin 11 for drain current measurement.
The Block Diagram for the simulation of the CMOS at one input is as follows. For an assigned input, the loop computes ID in sequence for the NMOS and PMOS, while iterating the output (drains) voltage. The loop halts when the currents are equal.
Measured and simulated results are in the following. The parameters have been obtained by simulation, as in the clusters on the left.
With the CMOS circuit taken as a linear amplifier, we now evaluate the properties. From the CMOS simulation, we save the node voltages for the simulation. Then using the NMOS and PMOS model simulators the nominal gain is obtained in the output range with the slope in the saturation region (red line) for both transistors, in the example, -35. (The peak is higher but for an input of around 100mV, this number would be appropriate.) The simulators provide the output resistance, and those in parallel are also plotted as Ro. The forward transconductance is then obtained from the gain and Ro.
The standard configuration is as shown here, as taken from the Philips data sheet (link above). The bias resistor is large and sets the operating point. With a 5k load, the gain would be about 10. The average gm given in the data sheet for this supply voltage agrees with the results here.
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