Static CMOS measurements are made and compared with a simulation based on the strong inversion model, Level 3. The effect of the implant is included with an implant voltage, Vd, added to the flatband voltage. Beta (mobility) is assumed constant. The purpose of the implant is to move the effect threshold voltages of the NMOS (high) and PMOS (low) to a common value, such that the CMOS switching occurs near the middle of the voltage range.
The following link shows the derivation of Level 3. The original version is based on a current integration with the standard form for the depletion-region oxide voltage, which leads to a 3/2 power term in surface potential (level 2). For level 3, this is eliminated with a Taylor series expansion of the these terms. In this link, the expansion occurs, of the depletion-region expression, before the integration. The results are identical.
Parameters are extracted for the devices in the saturation mode. The simulation equations for this case are given in the following. The parameters are VTO, GAMMA, Beta (KP), in addition to KAPPA, as discussed below.
Using an initial guess for GAMMA and KAPPA, parameters VTo and Beta are determined from the intercept and slope of a straight-line curve fit as in the following.
The measured data, from the following circuit, are a transfer function over a range of drain current (sweep VG1) corresponding to nominal strong inversion and that representative of the CMOS switch. VD1=1V for all currents.
The LabVIEW VI block diagram for the extraction is as follows. XB is a global variable that contains the data. The ICON “FN Sig” computes the saturation region modulation factor and the ICON “FN PHI” calculates the intrinsic flatland voltage, VFB, based on GAMMA. The extraction of Beta and Vto is performed in a simple calculation by “FN_SIP_sub”. The pinchoff voltage VP used by “FN_sig” is also supplied by “FN_SIP_Sub”, as shown in the Formula Node below.
The resulting data and simulation for the transfer functions for the NMOS and PMOS are as follows. In each case, GAMMA is adjusted for a common Vd, which is known. The values for VFB, and thus Vd, as calculated are in error from the use of PHI, as the actual flatband voltage at the bias levels of the transfer characteristic is larger. The fact that the fit in the case of the PMOS is not precise is an indication of the fact that Beta is not constant. Also, VTo will be in error from the fact that the drain current is only marginally in a state of strong inversion and that diffusion current is not negligible. Thus the parameters are somewhat artificial (in terms of the physical association) but function as required.
The channel-length modulation function is as follows. The parameter is KAPPA. The above curve fit is obtained initially with a guess KAPPA and then repeated with an iteration.
The parameters from the above files are passed to the CMOS simulator by way of a Global Variable. These are then used in the simulator as shown below, along with measured data.
We now use the simulator to investigate the state of the two transistors at various points in the switching process. In the first step, the input is Vin=1.94 V, the NMOS is active with a “load” from the PMOS, which is in pre-sat. Vo=4.9 V. Solution is for equal drain currents for both devices.
In the following step, Vi=2.34 V, and Vo=3.1, such VSD for the PMOS is 1.9 V, i.e., both transistors are active. Most of the switching occurs in this mode.
We move on to the opposite state, thus where the switch output is near zero. The NMOS is now the “load”, in pre-saturation, and the PMOS is active. The following drain-current function is thus the transfer characteristic for the PMOS with VSD about 5V.
The following shows a sweep from output high to low. A significant current still flows with the output nearly full off. The solution in all cases is where the currents are equal. NMOS goes from low to high, while the PMOS goes from high to low.
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